(1) Field of the Invention
This invention relates to an output circuit for converting input charges into electrical voltage. More particularly, it relates to an output circuit, such as an initial stage output buffer of a charge transfer device, such as CCD imaging device or CCD delay device.
(2) Description of the Prior Art
In CCD imaging or CCD delay devices, an output circuit for outputting signal charges is formed on a chip for converting minute input electrical charges into electrical voltage.
FIG. 1 shows an example of a customary output circuit in which a transfer electrode 102 for transferring electrical charges and an output gate 103 are formed on a substrate 101. A floating diffusion region 104 for storage of signal charges is disposed between the output gate 103 and a precharging gate 105 and connected to a gate of an nMOS transistor 106 constituting an initial stage source follower of the output circuit. With this initial stage source follower, a ground voltage GND is applied via a constant current source 107 to the source of the nMOS transistor 106, the drain of which is supplied with a source voltage V.sub.DD. The output of this initial stage source follower is provided from the source of nMOS transistor 106 and input to the gate of an nMOS transistor 108 constituting the next stage buffer. A constant current source 109 is similarly connected to the source of the nMOS transistor 108, from which an output signal V.sub.out is provided.
There is also known a prior art device in which the floating diffusion region 104 is replaced by a floating gate from which electrical charges are supplied to a source follower so as to be converted into an electrical voltage.
In these output circuits, conversion from minute electrical charges into electrical voltage is carried out and, the larger the charge to voltage conversion gain, the higher is the S/N ratio of the circuit.
Meanwhile, from the well-known relation Q=V.times.C, where V represents electrical voltage, Q electrical charges and C electrical capacitance, an output circuit with a lesser electrical capacitance is preferred because lesser electrical charges suffice to produce desired electrical voltage.
Above all, as shown in FIG. 2, the following relation EQU C.sub.tot =C.sub.FD +C.sub.S +C.sub.GD
where C.sub.tot represents total capacitance, C.sub.FD the capacitance between the floating diffusion region and the substrate, C.sub.s the wiring capacity and C.sub.GD the gate-to-drain capacitance of the nMOS transistor, holds from the floating diffusion region 110 to the first stage source follower nMOS transistor 111. Above all, it is required from circuit characteristics to reduce the capacitance C.sub.GD which depends upon the gain-to-drain overlap of the nMOS transistor which is supplied with a signal V.sub.sig.